1. Field of the Invention
The present invention relates to a level shifter circuit.
2. Description of the Related Art
A large-scale semiconductor integrated circuit (LSI) that operates at voltage lower than that of an external circuit is supplied with a low-voltage power supply VDD1 for an internal circuit and a high-voltage power supply VDD2 for interface with the external circuit. A level shifter circuit that converts (boosts) a voltage level is provided in an interface circuit that outputs a signal generated by the internal circuit, which operates with the low-voltage power supply VDD1, to the external circuit, which operates with the high-voltage power supply VDD2.
In the level shifter circuit, in general, two series circuits of PMOS transistors and NMOS transistors are provided in parallel between the high-voltage power supply VDD2 and a circuit ground GND (hereinafter, “GND”). With the two NMOS transistors on the GND side set as a differential pair, two signals having a complementary relation by the low-voltage power supply VDD1 are respectively applied to gates of the NMOS transistors. Between the two PMOS transistors on the power supply VDD2 side, a gate of one PMOS transistor is connected to a drain of the other PMOS transistor and a drain of one PMOS transistor is connected to a gate of the other PMOS transistor. A signal by the power supply VDD2 corresponding to a signal by the power supply VDD1 input to one of the differential pair is output from a drain connecting end of one of the series circuits (see, for example, JP-A 2000-174610 (KOKAI) (FIG. 13)).
The level shifter circuit has a characteristic that, when the voltage of the power supply VDD1 drops and signal amplitude (a voltage level) of an input signal falls, the ability of the two NMOS transistors, which form the differential pair, for driving the two PMOS transistor falls and a propagation delay between an input and an output increases and, when the signal amplitude further falls to near a threshold value, propagation is exponentially delayed. This delay characteristic can be improved if threshold voltage of the two NMOS transistors is reduced. However, this causes an increase in a leak current. An increase in process steps for reducing the threshold voltage causes an increase in manufacturing cost.
In an LSI in recent years, power supply voltage (VDD1) of an internal circuit is steadily reduced according to requests for refining and lower power consumption. On the other hand, interface voltage (VDD2) with the outside of the LSI is not reduced at all because, for example, the interface voltage is decided by a standard and the like. Therefore, a potential difference between the power supply voltage (VDD1) of the internal circuit and the interface voltage (VDD2) with the outside of the LSI increases as the generation of the LSI descends. The problem of deterioration in the delay characteristic tends to become more serious.